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wireless components ask/fsk 915mhz single conversion receiver tda 5212 version 1.3 specification december 2006
edition 12.06 published by infineon technologies ag, am campeon 1-12, 85579 neubiberg ? infineon technologies ag december 2006. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits im- plemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous su bstances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? - 2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. revision history current version: 1.3 as of 12.12.06 previous version: 1.2 page (in previous version) page (in current version) subjects (major changes since last revision) 3-4, 5-12 3-4, 5-12 correction of some typing mistakes product info, 2-3 product info, 2-3 change of package name to pg-tssop-28
product info product info wireless components specification, december 2006 package tda 5212 product info general description the ic is a very low power consump- tion single chip fsk/ask superhet- erodyne receiver (shr) for the re- ceive frequency range between 902 and 928 mhz that is pin compatible to the ask receiver tda5202. the ic offers a high level of integration and needs only a few external compo- nents. the device contains a low noise amplifier (lna), a double balanced mixer, a fully integrated vco, a pll synthesiser, a crystal oscillator, a lim- iter with rssi generator, a pll fsk demodulator, a data filter, a data com- parator (slicer) and a peak detector. additionally there is a power down fea- ture to save battery life. features low supply current (i s = 5.4 ma typ. in fsk mode, i s = 4.8 ma typ. in ask mode) supply voltage range 5 v 10% power down mode with very low supply current (90 na typ.) fsk and ask demodulation capa- bility fully integrated vco and pll synthesiser ask sensitivity better than -109 dbm over specified tempera- ture range (- 40 to +85c) receive frequency range 902 to 928 mhz limiter with rssi generation, operating at 10.7 mhz selectable reference frequency 2nd order low pass data filter with external capacitors data slicer with self-adjusting threshold fsk sensitivity better than -102 dbm over specified tempera- ture range (- 40 to +85c) application keyless entry systems remote control systems low bitrate ism-band communica- tion systems ordering information type ordering code package tda 5212 sp000013430 pg-tssop-28 samples available
1 table of contents 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-i 2 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -9 3.4 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.1 low noise amplifier (lna) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.2 mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.3 pll synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.4 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.5 limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.6 fsk demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.4.7 data filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4.8 data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4.9 peak detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4.10 bandgap reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -13
4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.1 choice of lna threshold voltage and time constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 data filter design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 crystal load capacitance calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4 crystal frequency calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5 data slicer threshold generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.6 ask/fsk switch functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.6.1 fsk mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.6.2 ask mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.7 principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 1 5 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 2 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3 test board layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10 5.4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 6 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -i 7 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-i
2 product description 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 contents of this chapter
product description 2 - 2 tda 5212 wireless components specification, december 2006 2.1 overview the ic is a very low power consumption single chip fsk/ask superheterodyne receiver (shr) for receive frequencies between 902 and 928 mhz that is pin compatible to the ask receiver tda5202. the ic offers a high level of integra- tion and needs only a few external components. the device contains a low noise amplifier (lna), a double balanced mixer, a fully integrated vco, a pll synthesiser, a crystal oscillator, a limiter with rssi generator, a pll fsk demodulator, a data filter, a data comparator (slicer) and a peak detector. addi- tionally there is a power down feature to save battery life. 2.2 application keyless entry systems remote control systems low bitrate ism-band communication systems 2.3 features low supply current (i s = 5.4 ma typ.fsk mode, 4.8 ma typ. ask mode) supply voltage range 5v 10% power down mode with very low supply current (90na typ.) fsk and ask demodulation capability fully integrated vco and pll synthesiser rf input sensitivity ask -112dbm typ. at 25c, better than -109dbm over complete specified operating temperature range (-40 to +85c) rf input sensitivity fsk -105dbm typ. at 25c, better than -102dbm over complete specified operating temperature range (-40 to +85c) receive frequency range between 902 and 928 mhz selectable reference frequency limiter with rssi generation, operating at 10.7mhz 2nd order low pass data filter with external capacitors data slicer with self-adjusting threshold
product description 2 - 3 tda 5212 wireless components specification, december 2006 2.4 package outlines p_tssop_28.eps figure 2-1 pg-tssop-28 package outlines
3 functional description 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 contents of this chapter
functional description 3 - 2 tda 5212 wireless components specification, december 2006 3.1 pin configuration pin_configuration_5212_v1.0.wmf figure 3-1 ic pin configuration crst2 pdwn pdo data 3vout thres ffb opp sln slp limx lim csel msel crst1 vcc lni tagc agnd lno vcc mi mix agnd fsel ifo dgnd vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 tda 5212
functional description 3 - 3 tda 5212 wireless components specification, december 2006 3.2 pin definition and function table 3-1 pin definition and function pin no. symbol equivalent i/o-schematic function 1 crst1 external crystal connector 1 2 vcc 5v supply 3 lni lna input 4.15v 50ua 1 57ua 4k 1k 3 500ua
functional description 3 - 4 tda 5212 wireless components specification, december 2006 6 1k 5v 4 tagc agc time constant control 5 agnd analogue ground return 6 lno lna output 7 vcc 5v supply 8 9 mi mix mixer input complementary mixer input 10 agnd analogue ground return 11 buf mixer buffer ground 1k 4.2ua 1.5ua 1.7v 4.3v 4 6 1k 5v 8 1.7v 9 400ua 2k 2k
functional description 3 - 5 tda 5212 wireless components specification, december 2006 2.2v 4.5k 60 12 300ua 12 ifo 10.7 mhz if mixer output 13 dgnd digital ground return 14 vdd 5v supply (pll counter cir- cuitry) 15 msel ask/fsk modulation format selector 16 csel 7.xx or 14.xx mhz quartz selector 2.2v 4.5k 60 12 300ua 15 1.2v 3.6k 1.2v 80k 16
functional description 3 - 6 tda 5212 wireless components specification, december 2006 17 18 lim limx limiter input complementary limiter input 19 slp data slicer positive input 20 sln data slicer negative input 330 15k 15k 18 17 2.4v 75ua 19 80a 15ua 3k 100 5ua 20 10k
functional description 3 - 7 tda 5212 wireless components specification, december 2006 21 opp opamp noninverting input 22 ffb data filter feedback pin 23 thres agc threshold input 24 3vout 3v reference output 21 200 5ua 100k 5ua 22 10k 5ua 23 3.1v 24 20k ?
functional description 3 - 8 tda 5212 wireless components specification, december 2006 25 data data output 26 pdo peak detector output 27 pdwn power down input 28 crst2 external crystal connector 2 25 500 40k 26 200 27 220k 220k 4.15v 50ua 28
functional description 3 - 9 tda 5212 wireless components specification, december 2006 3.3 functional block diagram functional_diagram_5212.wmf figure 3-2 main block diagram pdo buf vco : 128 / 64 det crystal osc data crystal pdwn csel buf loop filter bandgap reference u ref lna rf - + slicer tagc tda 5212 tda 5212 tda 5212 vcc vcc agnd agc reference thres 3vout fsk pll demod ota peak detector lni dgnd - + mix lno mi opp ffb slp vcc lim limx if filter ifo sln msel limiter 68912 1718 22 21 19 20 25 26 23 24 3 4 14 13 2,7 5,10 11 15 16 1 28 27 - + ask fsk op + -
functional description 3 - 10 tda 5212 wireless components specification, december 2006 3.4 functional blocks 3.4.1 low noise amplifier (lna) the lna is an on-chip cascode amplifier with a voltage gain of 15 to 20db. the gain figure is determined by the external matching networks situated ahead of lna and between the lna output lno (pin 6) and the mixer inputs mi and mix (pins 8 and 9). the noise figure of the lna is approximately 2db, the current consumption is 500a. the gain can be reduced by approximately 18db. the switching point of this agc action can be determined externally by applying a threshold voltage at the thres pin (pin 23). this voltage is compared internally with the received signal (rssi) level generated by the limiter circuitry. in case that the rssi level is higher than the threshold voltage the lna gain is reduced and vice versa. the threshold voltage can be generated by attaching a voltage divider between the 3vout pin (pin 24) which provides a temperature stable 3v output generated from the internal bandgap voltage and the thres pin as described in section 4.1. the time constant of the agc action can be deter- mined by connecting a capacitor to the tagc pin (pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operat- ing case and interference scenario to be expected during operation. the opti- mum choice of agc time constant and the threshold voltage is described in section 4.1. 3.4.2 mixer the double balanced mixer downconverts the input frequency (rf) in the range of 902 to 928 mhz to the intermediate frequency (if) at 10.7mhz with a voltage gain of approximately 18 db. a low pass filter with a corner frequency of 20mhz is built on chip in order to suppress rf signals to appear at the if out- put ( ifo pin). the if output is internally consisting of an emitter follower that has a source impedance of approximately 330 ? to facilitate interfacing the pin directly to a standard 10.7mhz ceramic filter without additional matching cir- cuitry. 3.4.3 pll synthesizer the phase locked loop synthesiser consists of a vco, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. the vco is including spiral inductors and varactor diodes. the oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer via a buffer amplifier. the buf pin (pin 11) has to be tied to ground. no additional components are necessary. the loop filter is also realised fully on-chip. using high side injection of the local oscillator (l0) for receiving frequencies below 921mhz and low side injection for frequencies above 921mhz, the receiving frequency band of 902 to 928mhz can be covered due to the l0 fre-
functional description 3 - 11 tda 5212 wireless components specification, december 2006 quency band of 910 to 932mhz. but please note that using high side injetion of the l0 yields a sign inversion of the demodulated data signal in case of fsk. see also section 4.4. 3.4.4 crystal oscillator the on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 7 and 14mhz range as the overall division ratio of the pll can be switched between 64 and 128 via the csel (pin 16 ) pin according to the following table. the calculation of the value of the necessary quartz load capacitance is shown in section 4.3, the quartz frequency calculation is expained in section 4.4. 3.4.5 limiter the limiter is an ac coupled multistage amplifier with a cumulative gain of approximately 80db that has a bandpass-characteristic centred around 10.7mhz. it has an input impedance of 330 ? to allow for easy interfacing to a 10.7mhz ceramic if filter. the limiter circuit acts as a receive signal strength indicator (rssi) generator which produces a dc voltage that is directly propor- tional to the input signal level as can be seen in figure 4.2. this signal is used to demodulate the ask receive signal in the subsequent baseband circuitry and to turn down the lna gain by approximately 18db in case the input signal strength is too strong as described in section 3.4.1 and section 4.1. 3.4.6 fsk demodulator to demodulate frequency shift keyed (fsk) signals a pll circuit is used that is contained fully on chip. the limiter output differential signal is fed to the linear phase detector as is the output of the 10.7mhz center frequency vco. the demodulator gain is typically 200v/khz. the passive loop filter output that is comprised fully on chip is fed to both the vco and the modulation format switch.this signal is representing the demodulated signal. this switch is actu- ally a switchable amplifier with an ac gain of 11 that is controlled by the msel table 3-2 csel pin operating states csel crystal frequency open 7.xx mhz shorted to ground 14.xx mhz
functional description 3 - 12 tda 5212 wireless components specification, december 2006 pin (pin 15) as shown in the following table. this gain was chosen to facilitate detection in the subsequent circuits. the dc gain is 1 in order not to saturate the subsequent data filter wih the dc offset produced by the demodulator in case of large frequency offsets of the if signal. the resulting frequency characteristic and details on the principle of operation of the switch are described in section 4.6. the demodulator circuit is switched off in case of reception of ask signals. 3.4.7 data filter the data filter comprises an op-amp with a bandwidth of 100khz used as a voltage follower and two 100k ? on-chip resistors. along with two external capacitors a 2nd order sallen-key low pass filter is formed. the selection of the capacitor values is described in section 4.2. 3.4.8 data slicer the data slicer is a fast comparator with a bandwidth of 100 khz. this allows for a maximum receive data rate of approximately 120kbaud. the maximum achievable data rate also depends on the if filter bandwidth and the local oscil- lator tolerance values. both inputs are accessible. the output delivers a digital data signal (cmos-like levels) for the detector. the self-adjusting threshold on pin 20 its generated by rc-term or peak detector depending on the baseband coding scheme. the data slicer threshold generation alternatives are described in more detail in section 4.5. 3.4.9 peak detector the peak detector generates a dc voltage which is proportional to the peak value of the receive data signal. an external rc network is necessary. the input is connected to the output of the rssi-output of the limiter, the output is con- nected to the pdo pin (pin 26 ). this output can be used as an indicator for the received signal strength to use in wake-up circuits and as a reference for the data slicer in ask mode. note that the rssi level is also output in case of fsk mode. table 3-3 msel pin operating states msel modulation format open ask shorted to ground fsk
functional description 3 - 13 tda 5212 wireless components specification, december 2006 3.4.10 bandgap reference circuitry a bandgap reference circuit provides a temperature stable reference voltage for the device. a power down mode is available to switch off all subcircuits which is controlled by the pwdn pin (pin 27) as shown in the following table. the sup- ply current drawn in this case is typically 90na. table 3-4 pdwn pin operating states pdwn operating state open or tied to ground powerdown mode tied to vs receiver on
4 applications 4.1 choice of lna threshold voltage and time constant . . . . . . . . . . . . 4-2 4.2 data filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 crystal load capacitance calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4 crystal frequency calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5 data slicer threshold generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.6 ask/fsk switch functional description . . . . . . . . . . . . . . . . . . . . . . 4-8 4.7 principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 contents of this chapter
applications 4 - 2 tda 5212 wireless components specification, december 2006 4.1 choice of lna threshold voltage and time constant in the following figure the internal circuitry of the lna automatic gain control is shown. lna_autom.wmf figure 4-1 lna automatic gain control circuitry the lna automatic gain control circuitry consists of an operational transimpe- dance amplifier that is used to compare the received signal strength signal (rssi) generated by the limiter with an externally provided threshold voltage u thres . as shown in the following figure the threshold voltage can have any value between approximately 0.8 and 2.8v to provide a switching point within the receive signal dynamic range. this voltage u thres is applied to the thres pin (pin 23) the threshold voltage can be generated by attaching a voltage divider between the 3vout pin (i.e. pin 24) which provides a temperature stable 3v output generated from the inter- nal bandgap voltage and the thres pin. if the rssi level generated by the limiter is higher than u thres , the ota generates a positive current i load . this yields a voltage rise on the tagc pin (pin 4). otherwise, the ota generates a negative current. these currents do not have the same values in order to achieve a fast-attack and slow-release action of the agc and are used to charge an external capacitor which finally generates the lna gain control volt- age. 4 lna rssi ( 0.8 - 2.8v) vcc gai n contr ol vol t ag e ota +3.1 v i lo ad rssi > u th r e s h o ld : i load =4.2a rssi < u th r e s h o ld : i load = -1.5a u c c u c :< 2.6v : gai n hi g h u c :> 2.6v : gai n l ow u cmax = v cc - 0.7v u cmin = 1.67v r1 r2 pi ns: 24 23 u threshold 20k ?
applications 4 - 3 tda 5212 wireless components specification, december 2006 rssi-agc.wmf figure 4-2 rssi level and permissive agc threshold levels the switching point should be chosen according to the intended operating sce- nario. the determination of the optimum point is described in the accompanying application note, a threshold voltage level of 1.8v is apparently a viable choice. it should be noted that the output of the 3vout pin is capable of driving up to 50a, but that the thres pin input current is only in the region of 40na. as the current drawn out of the 3vout pin is directly related to the receiver power con- sumption, the power divider resistors should have high impedance values. the sum of r1 and r2 has to be 600k ? in order to yield 3v at the 3vout pin. r1 can thus be chosen as 240k ? , r2 as 360k ? to yield an overall 3vout output current of 5a 1 and a threshold voltage of 1.8v note: if the lna gain shall be kept in either high or low gain mode this has to be accomplished by tying the thres pin to a fixed voltage. in order to achieve high gain mode operation, a voltage higher than 2.8v shall be applied to the thres pin, such as a short to the 3volt pin. in order to achieve low gain mode operation a voltage lower than 0.7v shall be applied to the thres , such as a short to ground. as stated above the capacitor connected to the tagc pin is generating the gain control voltage of the lna due to the charging and discharging currents of the ota and thus is also responsible for the agc time constant. as the charging and discharging currents are not equal two different time constants will result. the time constant corresponding to the charging process of the capacitor shall be chosen according to the data rate. according to measurements performed at infineon the capacitor value should be greater than 47nf. 1. note the 20k ? resistor in series with the 3.1v internal voltage source lna always in high gain mode 0 0.5 1 1.5 2 2.5 3 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 input level at lna input [dbm] u thres voltage range rssi level range lna always in low gain mode rssi level
applications 4 - 4 tda 5212 wireless components specification, december 2006 4.2 data filter design utilising the on-board voltage follower and the two 100k ? on-chip resistors a 2nd order sallen-key low pass data filter can be constructed by adding 2 exter- nal capacitors between pins 19 (slp) and 22 (ffb) and to pin 21 (opp) as depicted in the following figure and described in the following formulas 1 . filter_design.wmf figure 4-3 data filter design with the quality factor of the poles where in case of a bessel filter a = 1.3617, b = 0.618 and thus q = 0.577 and in case of a butterworth filter a = 1.141, b = 1 and thus q = 0.71 example: butterworth filter with f 3db = 5khz and r = 100k ? : c 1 = 450pf, c 2 = 225pf 1. taken from tietze/schenk: halbleiterschaltungstechnik, springer berlin, 1999 pins: 22 21 19 rr 100k 100k c 1 c 2 db f r b q c 3 2 2 1 = db f qr b c 3 4 2 = a b q =
applications 4 - 5 tda 5212 wireless components specification, december 2006 4.3 crystal load capacitance calculation the value of the capacitor necessary to achieve that the crystal oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in section 5.1.3 and by the crystal specifications given by the crystal manufacturer. quartz_load_5212.wmf figure 4-4 determination of series capacitance value for the crystal oscillator crystal specified with load capacitance with c l the load capacitance (refer to the crystal specification). examples: 7.2 mhz: c l = 12 pf x l =500 ? c s = 9.5 pf 14.5 mhz: c l = 12 pf x l =1050 ? c s = 5.6 pf these values may be obtained in high accuracy by putting two capacitors in series to the quartz, such as 18pf and 20pf in the 7.2mhz case and 18pf and 8.2pf in the 14.5mhz case. but please note that the calculated value for c s includes also all parasitic capacitors. c s crystal input impedance z 1-28 tda5212 pin 28 pin 1 l l s x f c c 2 1 1 + =
applications 4 - 6 tda 5212 wireless components specification, december 2006 4.4 crystal frequency calculation as mentioned in section 3.4.3 the local oscillator (uhf pll) signal has to be high-side injected for a rf below 921mhz and low-side injected for a rf above 921mhz into the downconverting mixer. thus the crystal frequency is calcu- lated by using the following formula: with ? rf .... receive frequency ? lo .... local oscillator (pll) frequency (? rf 10.7) ? qu .... crystal oscillator frequency r .... ratio of local oscillator (pll) frequency and crystal frequency as shown in the subsequent table. this yields the following calculation for a rf of 915mhz for instance: csel tied to gnd 1 : table 4-1 pll division ratio dependence on states of csel csel ratio r = (f lo /f qu ) open 128 gnd 64 1.in the infineon evalboard the l0 is used in low side injection mode and therefore crystal with 14.1296875mhz is used. but to guarantee the function over the whole temperature range the l0 has to be used in high side injection mode for a rf of 915mhz (see also vdo frequency range). r f f rf qu 7 . 10 = mhz mhz mhz f qu 4641 . 14 64 7 . 10 915 = + =
applications 4 - 7 tda 5212 wireless components specification, december 2006 4.5 data slicer threshold generation the threshold of the data slicer can be generated in two ways, depending on the signal coding scheme used. in case of a signal coding scheme without dc content such as manchester coding the threshold can be generated using an external r-c integrator as shown in figure 4-5. the time constant t a of the r- c integrator has to be significantly larger than the longest period of no signal change t l within the data sequence. for the calculation of the time constant t a please see application note ?tda521x_anv1.1.? chapter ?4.11. data slicer?. in order to keep distortion low, the minimum value for r is 20k ? . data_slice1.wmf figure 4-5 data slicer threshold generation with external r-c integrator another possibility for threshold generation is to use the peak detector in con- nection with two resistors and one capacitor as shown in the following figure. the component values are depending on the coding scheme and the protocol used. data_slice2.wmf figure 4-6 data slicer threshold generation utilising the peak detector pins: 20 19 r c 25 data out u threshold data slicer data filter pins: 20 19 25 data out u threshold data slicer data filter 26 peak detector c r r
applications 4 - 8 tda 5212 wireless components specification, december 2006 4.6 ask/fsk switch functional description the tda5211 is containing an ask/fsk switch which can be controlled via pin 15 (msel). this switch is actually consisting of 2 operational amplifiers that are having a gain of 1 in case of the ask amplifier and a gain of 11 in case of the fsk amplifier in order to achieve an appropriate demodulation gain character- istic. in order to compensate for the dc-offset generated especially in case of the fsk pll demodulator there is a feedback connection between the thresh- old voltage of the bit slicer comparator (pin 20) to the negative input of the fsk switch amplifier. this is shown in the figure below: ask_fsk_datapath.wmf figure 4-7 ask/fsk mode datapath 4.6.1 fsk mode the fsk datapath has a bandpass characterisitc due to the feedback shown above (highpass) and the data filter (lowpass). the lower cutoff frequency f2 is determined by the external rc-combination. the upper cutoff frequency f3 is determined by the data filter bandwidth. the demodulation gain of the fsk pll demodulator is 200v/khz. this gain is increased by the gain v of the fsk switch, which is 11. therefore the resulting dynamic gain of this circuit is 2.2mv/khz round about within the bandpass. the r 1 =100k r 2 =100k v = 1 19 r 4 =30k r 3 =300k data out ac dc typ. 2 v 1.5 v......2.5 v 0.18 mv/khz fsk pll demodulator rssi (ask signal) c 1 r ask/fsk switch ask fsk + - + - 22 25 c c 2 20 ask mode : v=1 fsk mode : v=11 21 15 msel ffb opp slp sln comp - + data filter
applications 4 - 9 tda 5212 wireless components specification, december 2006 gain for the dc content of fsk signal remains at 200v/khz. the cutoff fre- quencies of the bandpass have to be chosen such that the spectrum of the data signal is influenced in an acceptable amount. in case that the user data is containing long sequences of logical zeros the effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at the negative input of the slicer comparator (pin20) is used. the comparator has no hysteresis built in. this offset voltage is generated by the bias current of the negative input of the comparator (i.e. 20na) running over the external resistor r. this voltage raises the voltage appearing at pin 20 (e.g. 1mv with r = 100k ? ). in order to obtain benefit of this asymmetrical offset for the demodulation of long zeros the lower of the two fsk frequencies should be chosen in the transmitter as the zero- symbol frequency. in the following figure the shape of the above mentioned bandpass is shown. frequenzgang.wmf figure 4-8 frequency characterstic in case of fsk mode the cutoff frequencies are calculated with the following formulas: v 0db 3db v-3db f 20db/dec - 40db/dec f1 f2 f3 g ai n ( pi n19) dc 0.18mv/khz 2mv/khz c k r k r f ? + ? ? = 330 330 2 1 1
applications 4 - 10 tda 5212 wireless components specification, december 2006 f 3 is the 3db cutoff frequency of the data filter - see section 4.2. example: r = 100k ? c = 47nf this leads to f 1 = 44hz and f 2 = 485hz 4.6.2 ask mode in case the receiver is operated in ask mode the datapath frequency charac- tersitic is dominated by the data filter alone, thus it is lowpass shaped.the cutoff frequency is determined by the external capacitors c12 and c14 and the inter- nal 100k resistors as described in section 4.2 freq_ask.wmf figure 4-9 frequency charcteristic in case of ask mode 1 1 2 11 f f v f ? = ? = db f f 3 3 = 0db -3db f -40db/dec f3db
applications 4 - 11 tda 5212 wireless components specification, december 2006 4.7 principle of the precharge circuit in case the data slicer threshold shall be generated with an external rc network as described in section 4.5 it is necessary to use large values for the capacitor c attached to the sln pin (pin 20) in order to achieve long time constants. this results also from the fact that the choice of the value for r connected between the slp and sln pins (pins 19 and 20) is limited by the 330k ? resistor appear- ing in parallel to r as can be seen in figure 4-6. apart from this a resistor value of 100k ? leads to a voltage offset of 1mv at the comparator input as described in section 4.6.1. the resulting startup time constant 1 can be calculated with: in case r is chosen to be 100k ? and c is chosen as 47nf this leads to when the device is turned on this time constant dominates the time necessary for the device to be able to demodulate data properly. in the powerdown mode the capacitor is only discharged by leakage currents. in order to reduce the turn-on time in the presence of large values of c a pre- charge circuit was included in the tda5210 as shown in the following figure. precharge.wmf figure 4-10 principle of the precharge circuit ( ) c k r ? = 330 || 1 ( ) ms nf k nf k k 6 . 3 47 77 47 330 || 100 1 = ? = ? ? = i lo ad +3.1v 20k + - ota +2.4v r1 r2 24 23 u threshold c 0 / 240ua + - 20 19 r data filter ask/fsk switch c2 u2 us uc ucus u2<2.4v : i=240ua u2>2.4v : i=0 r1+r2=600k
applications 4 - 12 tda 5212 wireless components specification, december 2006 this circuit charges the capacitor c with an inrush current i load of 240a for a duration of t 2 until the voltage u c appearing on the capacitor is equal to the volt- age u s at the input of the data filter. this voltage is limited to 2.5v. as soon as these voltages are equal or the duration t 2 is exceeded the precharge circuit is disabled. 2 is the time constant of the charging process of c which can be calculated as as the sum of r1 and r2 is sufficiently large and thus can be neglected. t2 can then be calculated according to the following formula: the voltage transient during the charging of c2 is shown in the following figure: e-fkt1.wmf figure 4-11 voltage appearing on c2 during precharging process the voltage appearing on the capacitor c connected to pin 20 is shown in the following figure. it can be seen that due to the fact that it is charged by a con- stant current source it exhibits is a linear increase in voltage which is limited to 2 20 2 c k ? 6 . 1 3 4 . 2 1 1 ln 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? = v v t u2 2 3v 2.4v t2
applications 4 - 13 tda 5212 wireless components specification, december 2006 u smax = 2.5v which is also the approximate operating point of the data filter input. the time constant appearing in this case can be denoted as t3, which can be calculated with e-fkt2.wmf figure 4-12 voltage transient on capacitor c attached to pin 20 as an example the choice of c2 = 20nf and c = 47nf yields 2 = 0.4ms t 2 = 0.64ms t 3 = 0.49ms this means that in this case the inrush current could flow for a duration of 0.64ms but stops already after 0.49ms when the u smax limit has been reached. t3 should always be chosen to be shorter than t2. it has to be noted finally that during the turn-on duration t2 the overall device power consumption is increased by the 240a needed to charge c. the precharge circuit may be disabled if c2 is not equipped. this yields a t2 close to zero. note that the sum of r4 and r5 has to be 600k ? in order to pro- duce 3v at the thres pin as this voltage is internally used also as the refer- ence for the fsk demodulator. c a v a c u t s = = 240 5 . 2 240 3 max us t3 uc
5 reference 5.1 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3 test board layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 contents of this chapter
reference 5 - 2 tda 5212 wireless components specification, december 2006 5.1 electrical data 5.1.1 absolute maximum ratings warning the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic may result. table 5-1 absolute maximum ratings, ambient temperature t amb =-40c ... + 85c # parameter symbol limit values unit remarks min max 1 supply voltage v s -0.3 5.5 v 2 junction temperature t j -40 +125 c 3 storage temperature t s -40 +150 c 4 thermal resistance r thja 114 k/w 5 esd integrity, all pins v esd -1 +1 kv hbm according to mil std 883d, method 3015.7
reference 5 - 3 tda 5212 wireless components specification, december 2006 5.1.2 operating range within the operating range the ic operates as explained in the circuit descrip- tion. the ac/dc characteristic limits are not guaranteed. supply voltage: vcc = 4.5v .. 5.5v table 5-2 operating range, ambient temperature t amb = -40c ... + 85c # parameter symbol limit values unit test conditions/notes l item min max 1 supply current i sf i sa 6 5.4 ma ma f rf = 915mhz, fsk mode f rf = 915mhz, ask mode 2 receiver input level ask fsk, frequ. dev. 50khz rf in -109 -102 -13 -13 dbm dbm @ source impedance 50 ? , ber 2e-3, average power level, manchester encoded datarate 4kbit, 280khz if bandwidth 3 lni input frequency f rf 902 928 mhz 4 mi/x input frequency f mi 902 928 mhz 6 uhf local oscillator fre- quency range f lo 910 932 mhz 7 3db if frequency range f if -3db 5 23 mhz 8 powerdown mode on pwdn on 0 0.8 v 9 powerdown mode off pwdn off 2 v s v 10 gain control voltage, lna high gain state v thres 2.8 v s v 11 gain control voltage, lna low gain state v thres 0 0.7v v not part of the production test - either verified by design or measured in an infineon evalboard as described in section 5.2.
reference 5 - 4 tda 5212 wireless components specification, december 2006 5.1.3 ac/dc characteristics ac/dc characteristics involve the spread of values guaranteed within the spec- ified voltage and ambient temperature range. typical characteristics are the median of the production. the device performance parameters marked with are not part of the production test, but verified by design or measured in an infi- neon evalboard as described in section 5.2. table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v # parameter symbol limit values unit test conditions/ notes l item min typ max supply supply current 1 supply current, standby mode i s pdwn 90 120 na pin 27 (pdwn) open or tied to 0 v 2 supply current, device operating in fsk mode i sf 5.4 5.7 ma pin 11 (fsel) open, pin 15 (msel) tied to gnd 3 supply current, device operating in ask mode i sa 4.8 5.1 ma pin 11 (fsel) open, pin 15 (msel) open lna signal input lni (pin 3), v thres > 2.8v, high gain mode 1 average power level at ber = 2e-3 (sensitivity) ask rf in -112 dbm manchester encoded datarate 4kbit, 280khz if bandwidth 2 average power level at ber = 2e-3 (sensitivity) fsk rf in -105 dbm manchester enc. datarate 4kbit, 280khz if bandw., 50khz pk. dev. 3 input impedance, f rf = 915 mhz s 11 lna 0.717 / -78.4 deg 4 input level @ 1db c.p. f rf =915 mhz p1db lna -15 dbm 5 input 3 rd order intercept point f rf = 915 mhz iip3 lna -14 dbm f in = 914 & 916mhz 6 lo signal feedthrough at antenna port lo lni 73 dbm signal output lno (pin 6), v thres > 2.8v, high gain mode 1 gain f rf = 915 mhz s 21 lna 1.401 / 98.4 deg 2 output impedance, f rf = 915 mhz s 22 lna 0.869 / -25.7 deg
reference 5 - 5 tda 5212 wireless components specification, december 2006 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v (continued) # parameter symbol limit values unit test conditions/ notes l item min typ max 3 voltage gain antenna to ifo f rf = 915 mhz g antmi 40 db signal input lni, v thres = gnd, low gain mode 1 input impedance, f rf = 915 mhz s 11 lna 0.753 / -86.26 deg 2 input level @ 1db c. p. f rf = 915 mhz p1db lna -6 dbm signal input lni, v thres = gnd, low gain mode 3 input 3 rd order intercept point f rf = 915 mhz iip3 lna -5 dbm f in = 914 & 916mhz signal output lno, v thres = gnd, low gain mode 1 gain f rf = 915 mhz s 21 lna 0.174 / 107.4 deg 2 output impedance, f rf = 915 mhz s 22 lna 0.868 / -28.1 deg 3 voltage gain antenna to ifo f rf = 915 mhz g antmi 19 db signal 3vout (pin 24) 1 output voltage v 3vout 2.9 3 3.1 v i 3vout = 5a 2 current out i 3vout 50 a signal thres (pin 23) 1 input voltage range v thres 0 v s -1 v see section 4.1 2 lna low gain mode v thres 0 v 3 lna high gain mode v thres 3 v s -1 v or shorted to pin 24 4 current in i thres_in 5 na signal tagc (pin 4) 1 current out, lna low gain state i tagc_out 3.8 4.2 4.8 a rssi > v thres 2 current in, lna high gain state i tagc_in 11.5 2a rssi < v thres mixer signal input mi/mix (pins 8/9) 1 input impedance, f rf = 915 mhz s 11 mix 0.912 / -30.13 deg 2 input 3 rd order intercept point iip3 mix -25 dbm
reference 5 - 6 tda 5212 wireless components specification, december 2006 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v (continued) parameter symbol limit values unit test conditions/ notes l item min typ max signal output ifo (pin 12) 1 output impedance z ifo 330 ? 2 conversion voltage gain f rf =915 mhz g mix 18 db limiter signal input lim/x (pins 17/18) 1 input impedance z lim 264 330 396 ? 2 rssi dynamic range dr rssi 60 80 db 3 rssi linearity lin rssi 1 db 4 operating frequency (3db points) f lim 510.7 23 mhz data filter 1 useable bandwidth bw bb filt 100 khz slicer signal output data (pin 25) 1 useable bandwith bw bb slic 100 khz 2 capacitive loading of out- put c max slic 20 pf 3 low output voltage v slic_l 0 0.1 v 4 high output voltage v slic_h v s - 1.3 v s -1 v s -0.7 v output current= 200a slicer, sln (pin 20) 1 precharge current out i pch_sln -100 -220 -300 a see section 4.7 peak detector signal output pdo (pin 26) 1 low output voltage v slic_l 0 0.1 v 2 high output voltage v slic_h 2.9 3 3.1 v 3 load current i load -500 a static output cur- rent must not exceed -500a 4 leakage current i leakage 580 700 820 na
reference 5 - 7 tda 5212 wireless components specification, december 2006 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v (continued) parameter symbol limit values unit test conditions/ notes l item min typ max crystal oscillator signals crstl1, cristl 2, (pins 1/28) 1 operating frequency f crstl 6 15 mhz fundamental mode, series resonance 2 input impedance @ ~ 7.2mhz z 1-28 - 860 + j500 ? 3 input impedance @ ~ 14.5mhz z 1-28 - 550 + j1050 ? 4 serial capacity @ ~ 7.2mhz c s7 =c1 9.5 pf 5 serial capacity @ ~ 14.5mhz c s14 =c1 5.6 pf ask/fsk signal switch signal msel (pin 15) 1 ask mode v msel 1.4 4v or open 2 fsk mode v msel 0 0.2 v fsk demodulator 1 demodulation gain g fmdem 200 v/ khz 2 useable if bandwidth bw ifpll 10.2 10.7 11.2 mhz power down mode signal pdwn (pin 27) 1 powerdown mode on pwdn on 0 0.8 v 2 powerdown mode off pwdn off 2.8 v s v 3 input bias current pdwn i pdwn 19 a 4 start-up time until valid if signal is detected t su <1 ms note: startup - time is also depends on the used crystal pll divider signal csel (pin 16) 1 f crstl range 7.xxmhz v csel 1.4 4v or open
reference 5 - 8 tda 5212 wireless components specification, december 2006 table 5-3 ac/dc characteristics with t a 25 c, v vcc = 4.5 ... 5.5 v (continued) parameter symbol limit values unit test conditions/ notes l item min typ max 2 f crstl range 14.xxmhz v csel 0 0.2 v 3 input bias current csel i csel 5 a csel tied to gnd not part of the production test - either verified by design or measured in an infineon evalboard as described in section 5.2.
reference 5 - 9 tda 5212 wireless components specification, december 2006 5.2 test circuit the device performance parameters marked with in section 5.1.3 were either verified by design or measured on an infineon evaluation board. test_circuit.wmf figure 5-1 schematic of the evaluation board i n f i n e o n t e c h n o l o g i e s t i t l e : t d a 5 2 x x e v a l u a t i o n b o a r d f i l e : - 1 0 v 2 . 0 d a t e : j u l . 1 9 , 1 9 9 9
reference 5 - 10 tda 5212 wireless components specification, december 2006 5.3 test board layouts figure 5-2 top side of the evaluation board figure 5-3 bottom side of the evaluation board
reference 5 - 11 tda 5212 wireless components specification, december 2006 figure 5-4 component placement on the evaluation board
reference 5 - 12 tda 5212 wireless components specification, december 2006 5.4 bill of materials the following components are necessary for evaluation of the tda5212 at 915 mhz without use of a microchip hcs515 decoder. table 5-4 bill of materials ref value specification r1 100k ? 0805, 5% r2 100k ? 0805, 5% r3 820k ? 0805, 5% r4 240k ? 0805, 5% r5 360k ? 0805, 5% r6 10k ? 0805, 5% l1 3.3nh toko, ptl2012-f3n3c l2 3.9nh toko, ptl2012-f3n9c c1 1pf 0805, cog, 0.1pf c2 3.3pf 0805, cog, 0.1pf c3 4.7pf 0805, cog, 0.1pf c4 100pf 0805, cog, 5% c5 47nf 1206, x7r, 10% c6 3.3pf 0805, cog, 0.1pf c7 100pf 0805, cog, 5% c8 22pf 0805, cog, 5% c9 100pf 0805, cog, 5% c10 10nf 0805, x7r, 10% c11 10nf 0805, x7r, 10% c12 220pf 0805, cog, 5% c13 47nf 0805, x7r, 10% c14 470pf 0805, cog, 5% c15 47nf 0805, x7r, 10% c16 8.2pf 0805, cog, 1% c17 18pf 0805, cog, 0.25pf q1 14.129690mhz 1 jauch q 14.129690-s1 q2 sfe10.7ma5-a murata x2, x3 142-0701-801 johnson x1, x4, s1, s5 stl_2pol 2-pole pin connector s4 stl_3pol 3-pole pin connector, or not equipped ic1 tda 5212 infineon 1. 14.129690mhz crystals are used in the infineon evalboard, which means that the l0 is in low side injection mode (l0-frequency=904.3mhz). but to guarantee the function of the ic over the whole temperature range the l0 has to be used in high side rejection mode (l0-frequency=925.7mhz), therefore 14.4640625mhz crystals have to be used for a rf of 915mhz (see also vco-frequency range).
reference 5 - 13 tda 5212 wireless components specification, december 2006 the following components are necessary in addition to the above mentioned ones for evaluation of the tda5212 in conjunction with a microchip hcs512 decoder. table 5-5 bill of materials addendum ref value specification r21 22k ? 0805, 5% r22 10k ? 0805, 5% r23 22k ? 0805, 5% r24 820k ? 0805, 5% r25 560k ? 0805, 5% c21 100nf 1206, x7r, 10% c22 100nf 1206, x7r, 10% ic2 hcs512 microchip t1 bc 847b infineon d1 ls t670-jl infineon
list of figures list of figures - i tda 5212 wireless components specification, december 2006 6 list of figures figure 2-1 pg-tssop-28 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 figure 3-1 ic pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 figure 3-2 main block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 figure 4-1 lna automatic gain control circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 figure 4-2 rssi level and permissive agc threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 figure 4-3 data filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 figure 4-4 determination of series capacitance value for the crystal oscillator . . . . . . . . . . . . . 4-5 figure 4-5 data slicer threshold generation with external r-c integrator . . . . . . . . . . . . . . . . . . 4-7 figure 4-6 data slicer threshold generation utilising the peak detector . . . . . . . . . . . . . . . . . . . 4-7 figure 4-7 ask/fsk mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -8 figure 4-8 frequency characterstic in case of fsk mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 figure 4-9 frequency charcteristic in case of ask mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 figure 4-10 principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11 figure 4-11 voltage appearing on c2 during precharging proc ess . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 figure 4-12 voltage transient on capacitor c attached to pin 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 figure 5-1 schematic of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 figure 5-2 top side of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 10 figure 5-3 bottom side of the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 figure 5-4 component placement on the evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
list of tables list of tables - i tda 5212 wireless components specification, december 2006 7 list of tables table 3-1 pin definition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 table 3-2 csel pin operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -11 table 3-3 msel pin operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -12 table 3-4 pdwn pin operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3 table 5-1 absolute maximum ratings, ambient temperature t amb =-40c ... + 85c . . . . . . . . . 5-2 table 5-2 operating range, ambient temperature t amb = -40c ... + 85c . . . . . . . . . . . . . . . . . 5-3 table 5-3 ac/dc characteristics with ta 25 c, vvcc = 4.5 ... 5.5 v . . . . . . . . . . . . . . . . . . . . . 5-4 ac/dc characteristics with ta 25 c, vvcc = 4.5 ... 5.5 v (continued) 5-5 ac/dc characteristics with ta 25 c, vvcc = 4.5 ... 5.5 v (continued) 5-6 ac/dc characteristics with ta 25 c, vvcc = 4.5 ... 5.5 v (continued) 5-7 ac/dc characteristics with ta 25 c, vvcc = 4.5 ... 5.5 v (continued) 5-8 table 5-4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 table 5-5 bill of materials addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

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